Computer systems that comprise numerous storage elements often encounter problems during the initial power on procedure. When power is first applied to the system, the storage elements (flip-flops, registers, and memory arrays) begin in various random states. Some of these states will cause the system to operate incorrectly because of unanticipated interactions. Thus, the system would have to be shut down to clear the storage elements of the problematic state settings, and restart the system with different state settings that will hopefully not cause the system to lock up. This problem can occur with many home appliances such as CD players and VCR machines.
To obtain correct system initialization, a reset signal is invoked during start-up, such that the storage elements are all set to zero, or some benign initial state. However, as systems have become larger and larger, with more and more storage elements, then the reset signal cannot always be fanned out to all storage elements because of area and timing limitations. Thus, designers send the reset signal to the storage elements that can be reached within the fanout constraints. To reach the remaining elements, it requires several clock cycles with the reset signal active to achieve an acceptable start-up state in a correct design.
One prior art mechanism used to handle large system testing is to have two different simulation methods. One simulation method is event driven, which is used for diagnosis of design problems. The other is cycle based, which is much faster than the diagnosis oriented method, e.g. five to ten times faster, and is used for detection of design problems. Thus, when used together, the detection oriented method would determine which state would cause failure conditions, and the diagnosis oriented method would determine the reasons for failure. The detection oriented method gains speed by not accessing the internal states of the system model, e.g. the internal states of combination logic are not calculated during the simulation if it is part of an inactive path. The diagnosis oriented method could determine the reasons for failure because it can access the internal states.
A serious problem with this approach is reproducing or re-creating the faulting state detected by the cycle based or detection oriented method, for analysis by the event driven or diagnosis oriented method. This is particularly true if the states are generated in the detection oriented method by a random number generator. If a random number generator is used, then it is extremely difficult to re-create the precise faulting state. If the faulting state cannot be reproduced, then the diagnosis oriented method cannot accurately determine the reasons for failure.
Moreover, even if the cause of the failure has been determined or thought to be determined, then the prior art lacks a mechanism for verification that any changes to the design have resolved the failure. This is because even a small change to the design will cause large changes in the system initialization. Thus, it is essentially impossible to return to the state that caused the failure. In others the failing state cannot be duplicated so that the changes to the system cannot be verified.
Another prior art method is to test at the gate level, instead of at the register transfer level (RTL), and use a third logic value `X` in addition to 0 and 1. The X value could represent either a 0 or a 1 in the simulation of the design. However, the X state is pessimistic (i.e. shows problems that do not actually exist) in terms of reporting hang up conditions in the start-up state in logic simulation. Moreover, gate level simulation is generally about 3 to 10 times slower than RTL simulation, thus gate level simulation is undesirable because the simulations run slower. Furthermore, since a storage element can comprise many gates, and the gate design is much more complicated to work with than the register design. Thus, RTL level is more desirable. However, using the X state at the RTL level yields results that are even more pessimistic than at the gate level.
Therefore, there is a need in the art for a system that performs simulations at RTL level, and allows re-creation of a precise state out of thousands of randomly simulated states. Such a system would allow the proper operation of a tandem system using a fast detection oriented simulation method and a slower diagnosis oriented simulation method with full accessibility. Such a system would also allow for verification of any system design changes.